Need Independent Consultants only

·         Verilog is a MUST

·         UVM is a Nice to have

·         Duration is 6 months. If they’re doing well we’ll keep them longer

·         Location is Neenah and we need this person now

About the Role

Seeking a skilled Senior FPGA Verification Engineer for defining the verification methodology for complex FPGAs.  This person will create verification test plans and test cases, as well as architect and implement test benches to verify FPGA requirements.

Key Job Responsibilities

• Develop engineering/product concepts that are innovative, high-quality, cost-appropriate, and satisfy all stakeholder (customer, manufacturing, material, etc.) needs and requirements throughout the full Product Realization value stream
• Utilize appropriate tools and equipment to perform necessary design work including design creation, design analysis, and design verification
• Support proposal development through the identification of project tasks, durations, interdependencies, risks and assumptions
• Effectively work independently without direction from mentors of functional management
• Directly interface with customer to clearly and concisely communicate technical information

Skills & Abilities

·         Demonstrated history of verifying large, complex FPGA designs

·         Strong knowledge of revision control concepts and tools (ex. Subversion)

·         Ability to author verification plans and test cases

·         Working knowledge of coverage driven verification methodology, implementing functional and coverage assertions and working to close coverage

·         Ability to perform scripting (ex. Perl, Python, Tcl, Bash)

·         Ability to lead a small team of engineers through the FPGA development process, preferred

• Advanced abilities in mentorship and development of others

Education & Experience

·         A minimum of a Bachelor’s degree in Electrical Engineering or Computer Engineering  is required for this position

• 6+ years of verifying complex FPGAs using industry standard tools and methodologies is required, 8+ years is preferred.
• Extensive(5+yrs) experience in the following areas:
  • Using SystemVerilog and constrained random verification techniques