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Key Skills:
placement guidelines, clock-tree synthesis, routing, timing optimizations, (DRC/LVS/DFM, chip finishing)
Physical Design Engineer (Onsite)
Bay Area, CA
2021-10-01 12:58:00
2021-10-01 12:58:00
Job Type:
Contract
Location – Bay Area, CA
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· Hands-on experience with FinFET technologies is an advantage
Moiz
Email: moiz@ecomputertech.com
P: 972 996 2024 & 972-889-1818 x 106
Key Skills:
placement guidelines, clock-tree synthesis, routing, timing optimizations, (DRC/LVS/DFM, chip finishing)
